There is a continued demand for enhanced levels of safety related features within devices, such as microcontrollers, having one or more masters and one or more peripherals. Currently microcontrollers implement several layers of protection between the masters and the peripherals, particularly those affecting device Input/Output (I/O) directly. Current designs have protection through, for example, the use of user/supervisor level access rights, address range based protection through a Memory Protection Unit (MPU) and a Memory Management Unit (MMU), Master ID protection, and Process ID based protection. For example, U.S. Pat. No. 7,689,733 B2 describes a computer that operates in a metered mode for normal use and a restricted mode uses an input/output memory management unit (I/O MMU) in conjunction with a security policy to determine which peripheral devices are allowed direct memory access during the restricted mode of operation. U.S. Pat. No. 7,689,733 B2 describes that during restricted mode operation, non-authorized peripheral devices are removed from virtual address page tables or given vectors to non-functioning memory areas. However, known schemes may not always be sufficiently satisfactory. Safety concerns remain, such as erroneous operation of internal circuitry which may affect I/O in an unexpected and undesired manner. For example, a random soft error may cause disruption and potentially affect I/O and a continued wish for enhanced level of safety against unwanted behaviour persists. Current designs may still be compromised due to, for example, an access by a non-CPU master to areas of the device that may directly affect I/O, or an access that is not intended to occur but that results from a random soft error.